艾鍗學院 - FPGA/Verilog實戰教學

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課程大綱

從業界資深FPGA的工程研發及代理商FAE角度, 來看FPGA能耐與市場


	FPGA簡介		1) FPGA硬體架構 2) CPLD vs.FPGA 3) Vender {Altera, Xilinx, Lattice.} 主要Chip功能介紹與看懂規格

不只談Verilog 基本語法而是強調程式結構與重要語意，以及這些程式結構常被應用的地方。

Verilog

硬體描述語言

1) Verilog Tutorial

2) Verilog

a) combination design

b) synchronously design

c) over sampling design (rising & falling edge detect)

d) clock dividing (when clock frequency is lower than Altera PLL limitation)

e) Verilog "parameter" - one module with multi-function

3) Timing constraint Tutorial & Example

4) ModelSim Simulation Tutorial (Function Debugging)

5) Altera FPGA Tool (QuartsII) Tutorial

a) compiler, download, and programming.

b) debug tool tutorial. (SignalTap II,and In-System Sources and Probes)

c) TimeQuest Timing Analysis Report. (Timing constraint)

以業界最實務的技術作講解並教導如何實際撰寫verilog來實現這些功能！


	Lab 實作		1) MegaWizard – PLL, RAM, ROM, FIFO 2) Altera Signal Tap 3) Altera Source Probe 4) IIC Master & Slave interface implement & debugging 5) PWM 6) SPI Master & Slave interface implement & debugging 7) Altera TimeQuest & SDC (Synopsis Design Constraints) 8) VGA & OSD (On Screen Display) 9) Porting OpenCore (UART) 10) MegaWizard – Altera High Performance Controller – DDR2